Conventional data transition detect (DTD) circuits can terminate a bit line write signal after a constant delay. Such circuits can operate on a single transition of a data input and can allow write recovery to start without waiting until the end of an active write cycle. Provided that the user meets tSD (e.g., data setup to end-of-write), the correct data is written. A change in data input must start a new write pulse, regardless of when that change occurs.
Address transition detect (ATD) circuits can operate on external data pins to generate a global write pulse signal.
Another approach may be found in U.S. Pat. No. 5,751,644, entitled Data Transition Detect Write Control, is illustrated in FIG. 1 and is hereby incorporated by reference in its entirety. The latch R/S1 keeps the write driver (e.g., ND3 and ND4) enabled for writing either a data 0 or a data 1. When the signal WR.sub.-- 1 is equal to 1 and the signal WR.sub.-- 0 is equal to 0, the circuit is enabled for writing a 1. When the signal WR.sub.-- 1 is equal to 0 and the signal WR.sub.-- 0 is equal to 1, the circuit is enabled for writing a 0. For example, when writing 1, the write driver is initially enabled for writing a 1. The data makes a 0 to 1 transition and the signal WDATAB switches from 1 to 0. The data 1 is written into the memory array. The delayed 1 to 0 transition (e.g., the wdata delay) switches the latch R/S1 to be enabled for writing a 0 to end the write.
The main disadvantage of the circuit of FIG. 1 is that it may be vulnerable to data input DIN glitches that may lead to write failure in the memory cell. If the data first makes a transition from 0 to 1, and then from 1 to 0, the pulse width at data input DIN may be such that data is written into the memory cell, but cannot change the state of the latch R/S1 due to the filtering of the signal WDATA in the delay element. During such a condition, the write driver cannot write the new data 0, since it is still enabled for writing a 1. The same reasoning holds for the opposite data polarity.
The potential glitch condition may arise because the gates ND3 and ND4 are controlled by the two outputs of the same latch R/S1. There is no mechanism to keep the write driver enabled for either data polarity in the event of glitches or short pulses on data input signal DIN.